1. Field of the Invention
This invention relates to integrated circuits, and more particularly, the delivery of clock signals in integrated circuits.
2. Description of the Related Art
Modern integrated circuits (ICs) often times include structures known as clock trees for distribution and delivery of clock signals to synchronous circuits. Since a large number of circuits may utilize clock signals, clock trees can be large in many ICs. Due to the large size of clock trees can be a significant driver of power consumption. In some cases, a clock tree can consume 25% of the total power consumed by an IC.
Since the distribution and delivery of clock signals can be a significant driver in power consumption, various power saving techniques have been employed. One commonly used technique is clock gating. Using the technique of clock gating, a clock signal provided to a block of circuitry may be inhibited when the circuitry is idle. Clock gating may be performed at various levels of a clock tree. Fine-grain clock gating may be performed at the level of the clock consumer circuits themselves (e.g., flop circuits). Coarse clock gating may be performed at a higher level that is closer in the clock tree to the root clock signal.
Another common power saving technique involving clock signals is frequency scaling. In an IC that utilizes frequency scaling, a clock frequency may be increased for a heavier workload and reduced for a lighter workload. For example, in a processor having one or more processor cores, the frequency of a clock signal provided to a given core may be adjusted depending on the processing workload of that core. In some ICs, both clock gating and frequency scaling may be performed to provide even more control over the consumption of power incurred by distribution and delivery of clock signals.